The present invention relates to a dynamic memory circuit employing field effect transistors, and more particularly to a word line noise preventing circuit for preventing a word line from being affected by noise or the like.
Dynamic memories have been widely utilized in various fields because of large memory capacity and relatively low power consumption. In dynamic memories, word lines are driven in a dynamic manner. Namely, all word lines are reset to the ground potential in reset (or precharge) periods and, in active periods, a selected one word line is driven to a power voltage (Vcc) through a source-follower transistor while the remaining non-selected word lines are left in a floating state. In other words, the non-selected lines are not connected to any voltage source in active periods. Therefore, the non-selected word lines are easily affected by noise such as voltage change in digit lines. Particularly, rise of potential of digit lines having higher level (logic 1 level) to the power voltage Vcc by active pull up circuits raise the potential of the non-selected word lines. In this case, many memory cells which should not be selected are erroneously accessed so that a plurality of stored data are simultaneously read out to the each digit line, resulting in destruction of memory data stored in the memory cells.
In order to avoid the above problem due to the fluctuation in the potentials of the non-selected word lines, word line noise preventing circuits are provided to the respective word lines. The word line noise preventing circuit maintains the potential of the non-selected word line at the ground potential during active periods.
On the other hand, half the digit lines which have been charged to a precharge voltage, such as the power voltage during a reset period, are discharged to the ground potential by amplifying operation of sense amplifiers.
The discharge of the digit lines affects a potential of a substrate on which a memory is fabricated and potentials of memory cell capacitors through coupling therebetween so that the potentials of the substrate and the memory cell capacitors are lowered.
Especially, in the memory cell storing logic "0" level, i.e. the ground potential, the potential of the memory cell capacitors is lowered from the ground potential to a negative potential, and in the case where such negative potential is lower than the ground potential which is applied to the non-selected word lines by a threshold voltage of memory cell transistors, the memory cell transistors having gates coupled to the non-selected word lines become conducting. Thus, in addition to the memory cell transistors coupled to the selected word line, the memory cell transistors coupled to the non-selected word lines are erroneously rendered conductive, which means in other words a plurality of data from a plurality of memory cells are read out on the same digit line at the same time. Accordingly, data stored in these memory cells are destroyed due to mutual interference.